SC424MLTRT【PDF 25/29 页】IC REG DL BUCK/LINEAR 28MLPQ

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SC414/SC424

Applications Information (continued)

Using Ceramic Output Capacitors

When applications use ceramic output capacitors, the ESR

is normally too small to meet the previously stated ESR

criteria. In these applications it is necessary to add a small

virtual ESR network composed of two capacitors and one

resistor, as shown in Figure 14. This network creates a

ramp voltage across C

, analogous to the ramp voltage

generated across the ESR of a standard capacitor. This

ramp is then capacitively coupled into the FB pin via

capacitor C

OUT

Low-

side

High-

side

Figure 14 Virtual ESR Ramp Current

Output Voltage Dropout

The output voltage adjustable range for continuous-con-

duction operation is limited by the fi xed 320ns (typical)

minimum off -time. When working with low input volt-

ages, the duty-factor limit must be calculated using worst-

case values for on and off times.

The duty-factor limitation is shown by the next equation.

)

MIN

(

OFF

)

MIN

(

)

MIN

(

DUTY

The inductor resistance and MOSFET on-state voltage

drops must be included when performing worst-case

dropout duty-factor calculations.

System DC Accuracy V

OUT

Controller

Three factors aff ect V

OUT

accuracy: the trip point of the FB

error comparator, the ripple voltage variation with line

and load, and the external resistor tolerance. The error

comparator off set is trimmed so that under static condi-

tions it trips when the feedback pin is 750mV, 1%.

The on-time pulse from the SC414/SC424 in the design

example is calculated to give a pseudo-fi xed frequency of

250kHz. Some frequency variation with line and load is

expected. This variation changes the output ripple

voltage. Because constant on-time converters regulate to

the valley of the output ripple, ?of the output ripple

appears as a DC regulation error. For example, if the

output ripple is 50mV with V

= 6 volts, then the measured

DC output will be 25mV above the comparator trip point.

If the ripple increases to 80mV with V

= 25V, then the

measured DC output will be 40mV above the comparator

trip. The best way to minimize this eff ect is to minimize

the output ripple.

To compensate for valley regulation, it may be desirable to

use passive droop. Take the feedback directly from the

output side of the inductor and place a small amount of

trace resistance between the inductor and output capaci-

tor. This trace resistance should be optimized so that at

full load the output droops to near the lower regulation

limit. Passive droop minimizes the required output capaci-

tance because the voltage excursions due to load steps

are reduced as seen at the load.

The use of 1% feedback resistors may result in up to an

additional 1% error. If tighter DC accuracy is required,

resistors with lower tolerances should be used.

The output inductor value may change with current. This

will change the output ripple and therefore will have a

minor eff ect on the DC output voltage. The output ESR

also aff ects the output ripple and thus has a minor eff ect

on the DC output voltage.

Switching Frequency Variations

The switching frequency will vary depending on line and

load conditions. The line variations are a result of fi xed

propagation delays in the on-time one-shot, as well as

unavoidable delays in the external MOSFET switching. As

increases, these factors make the actual DH on-time

slightly longer than the ideal on-time. The net eff ect is

that frequency tends to falls slightly with increasing input

voltage.

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